Oxide layer uniformity is important in several applications in forming semiconductor devices. The uniformity of oxide layers can be affected by a number of processing variables. Processes such as the rate and uniformity of thermal oxide growth may be affected by the nature of the underlying layer and adjacent layers. Other processes including chemical mechanical polishing may undesirably cause variations in topography of a planarized surface due to preferential polishing of different materials making up portions of a semiconductor device polishing surface. As a result of oxide layer thickness nonuniformity, for example, where the oxide layer is used as an etching hardmask, subsequent processes such as etching may result in undesirable etching of selected portions of the semiconductor device leading to degraded performance of the completed semiconductor device.
For example, one group of semiconductor devices where the thickness uniformity of oxide layers is extremely important are flash memory devices. For example, in flash EEPROM (Electrically Erasable Programmable Read Only Memories), for example including polysilicon source and word lines, the level of the voltage required to be applied to word or source lines, (e.g., Vss) applied to a source line to accomplish erase operations, is critical and is affected by oxide layer thickness and uniformity. For example, small changes in the contact resistant (e.g., Rss) at an electrical contact portion of the polysilicon gate of a source or word line may adversely affect both write and erase operations including altering hot electron injection processes or Fowler-Nordheim tunneling processes at the gate electrode, both processes essential to the reliable operation of the flash memory devices. For example the electric field strength within a polysilicon gate in combination with the properties of the gate oxide, also referred to as a tunnel oxide, determine the desired flow of current in response to applied voltages to accomplish write and erase operations.
For example in the formation of polysilicon word and source lines in the formation of EEPROM memory cells, for example employing a self-aligned word line, an oxide hardmask is thermally grown over exposed polysilicon portions prior to an etching process to form the polysilicon structures. Some problems with prior art processing approaches have emerged including a lack in uniformity of the oxide hardmask. As a result, in subsequent etching processes, the hardmask is penetrated prematurely and undesirable etching of underlying polysilicon structures takes place degrading electrical performance of the memory device. Approaches to solve the problem including forming a thicker oxide layer hardmask to prevent premature etching breakthrough have had the undesired effect of increasing an electrical contact resistance to the polysilicon structure thereby also degrading electrical performance of the memory device. In addition, other processing approaches have been found or are believed to contribute to unacceptable behavior of the oxide hard mask layer, requiring novel processing approaches to achieve acceptable memory device behavior.
There is therefore a need in the flash memory device processing art to develop novel processing methods to improve the yield and reliability of flash memory devices including forming an oxide hardmask with optimal etching resistance and electrical contact resistance.
It is therefore an object of the invention to provide novel processing methods to improve the yield and reliability of flash memory devices including forming an oxide hardmask with optimal etching resistance and electrical contact resistance, while overcoming other deficiencies and shortcomings of the prior art.